The use and application of computer graphics to all kinds of systems and subsystems environments continues to increase to an even greater extent with the availability of faster and faster information processing and retrieval devices. The relatively higher speed of operation of such devices remains a high priority design objective. This is especially true in a graphics system, and even to a greater extent with "3D" graphics systems. Such graphics systems require a great deal of processing for huge amounts of data and the speed of data flow is critical in providing a marketable new product or system, or in designing graphics or other subsystems which may enable and drive new computer applications.
In most data and information processing systems, and especially in computer graphics systems, much time is consumed in accessing data from a memory or storage location, then processing that information and sending the processed information to another location for subsequent access, processing and/or display. As the speed of new processors continues to increase, access time for accessing and retrieving data from memory is becoming more and more of a bottleneck relative to available system speed. Subsystems such as graphics systems must be capable of performing more sophisticated functions in less time in order to process greater amounts of graphical data required by modern software applications. Thus, there is a continuing need for improvements in software methods and hardware implementations to accommodate operational speeds required by an expanding array of highly desired graphics applications and related special video effects.
In modern graphics systems, texture maps are implemented to provide extremely detailed and rich graphics images through the rendering of graphics objects. Texture maps are comprised of texels which are stored and accessed from memory, and rendered in the form of a composite of primitives or graphics objects on a display screen in response to a graphics application program. In general, the more intricate graphics representations require an enormous amount of detail and data to draw upon from the stored texture maps. Advanced graphics programs include mechanisms by which blocks of such data which are more frequently fetched by the program are stored in a relatively fast local memory. In most systems the local memory capacity is limited and much if not most of the texel map data storage is handled by the host system memory. Since the host system memory is generally relatively slower than the local graphics system memory, systems requiring a greater number of accesses to the host memory will be necessarily slower. Accordingly, the more desirable and robust graphics applications, which have more extensive and detailed texture maps will have more data traffic between the host system memory and the graphics device, which will slow down the system operation and tend to detract from the desirability of the more intricate and robust graphics applications.
In general, a high volume of access commands and data traffic between a graphics device and a host system memory causes memory access and data transfer delays which, in turn, result in an overall degradation of system speed. Much of this delay results from latency incurred through normal system CPU processing. Since each access to the system or host memory has required CPU processing, such requests cannot be met immediately if the CPU is occupied with other higher priority system tasks. Moreover, when the subsystem requests to the system CPU are sequential and conditioned upon the prior subsystem request being completed, additional system delays and CPU wait conditions are introduced. Much of the information transfer delay time may be also be obviated by an improved information transfer implementation which makes greater use of parallel or asynchronous information processing techniques. Accordingly, there is a need for an enhanced method and processing apparatus which is effective to improve the speed and efficiency of information transfers between a graphics device and a host memory and to reduce system CPU time usage and participation in such transfers.